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* Refresh fileenv patch for U-Boot 2025.01 * Update Tinker to U-Boot 2025.01 Needs minor patch adjustment, also fixed patch numbering. * Update ODROID-N2 to U-Boot 2025.01, move eMMC patch Move the patch for eMMC so it's applied only for N2 specifically and update it for 2025.01. * Update ODROID-C/XU to U-Boot 2025.01 No changes in patches necessary after moving the N2 patch. * Update RPi boards to U-Boot 2025.01 Changes needed in bcmstb PCIe driver due to upstream refactoring, rest only refreshed. All patches now target the same version, so we can drop one of the series. * Update VIM3 to U-Boot 2025.01 No patches here, just version bump. * Update Green to U-Boot 2025.01 Updated and refreshed patches, added a patch to disable OF_UPSTREAM which is now needed. * Update ODROID-M1 to U-Boot 2025.01 Drop patch that has been mostly merged upstream. The change is that HS400 would stay enabled but let's get back to what upstream does. * Update ODROID-M1 to U-Boot 2025.01 Drop all patches as M1S support should be now merged to U-Boot and DTS taken from upstream. * Disable DFU and mkeficapsule to fix build mkeficapsule requires gnutls to be built first but it's not among dependencies. Since we don't need the tool, we can disable it. DFU is also not used on HAOS and it implies EFI_LOADER that we already disable. Moreover, that also sets SET_DFU_ALT_INFO and leads to linker failure on some platforms where it's not implemented. * fixup! Update Green to U-Boot 2025.01 There were more changes needed in the Green config to use correct memory layout due to upstream changes, otherwise we'll have malloc failures in U-Boot proper. * Move N2 eMMC patch to more generic patches-meson To stay on the safe side, move the eMMC hack to more generic folder that's used for all targets using the meson_gx eMMC driver (i.e. C2, C4 and N2). This is still better than keeping it in hardkernel/patches which is applied only to some hardkernel boards (like it was before bump to U-Boot 20205.01).
146 lines
4.3 KiB
Diff
146 lines
4.3 KiB
Diff
From ad9ce9d8ba273fffeff3d98ae1fc978dd217ab1d Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= <sairon@sairon.cz>
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Date: Mon, 30 Sep 2024 17:56:45 +0200
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Subject: [PATCH] reset: reset-brcmstb: Add Broadcom STB reset controller
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driver
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add driver for the brcm,brcmstb-reset compatible used on RPi 5 by
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porting the upstream Linux driver. Assert/deassert functions are adapted
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to the U-Boot way of handling individual resets' IDs.
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Signed-off-by: Jan Čermák <sairon@sairon.cz>
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---
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drivers/reset/Kconfig | 6 +++
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drivers/reset/Makefile | 1 +
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drivers/reset/reset-brcmstb.c | 89 +++++++++++++++++++++++++++++++++++
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3 files changed, 96 insertions(+)
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create mode 100644 drivers/reset/reset-brcmstb.c
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diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
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index fe5c1214f57..186dd963bc4 100644
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--- a/drivers/reset/Kconfig
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+++ b/drivers/reset/Kconfig
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@@ -63,6 +63,12 @@ config RESET_BCM6345
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help
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Support reset controller on BCM6345.
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+config RESET_BRCMSTB
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+ bool "Broadcom STB reset controller"
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+ help
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+ This enables the reset controller driver for Broadcom STB SoCs using
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+ a SUN_TOP_CTRL_SW_INIT style controller.
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+
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config RESET_UNIPHIER
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bool "Reset controller driver for UniPhier SoCs"
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depends on ARCH_UNIPHIER
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diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
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index d99a78c9828..8d9181e8af7 100644
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--- a/drivers/reset/Makefile
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+++ b/drivers/reset/Makefile
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@@ -13,6 +13,7 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
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obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
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obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
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obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
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+obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
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obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
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diff --git a/drivers/reset/reset-brcmstb.c b/drivers/reset/reset-brcmstb.c
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new file mode 100644
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index 00000000000..c0aef5f1241
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--- /dev/null
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+++ b/drivers/reset/reset-brcmstb.c
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@@ -0,0 +1,89 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Broadcom STB generic reset controller for SW_INIT style reset controller
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+ *
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+ * Based on upstream Linux driver:
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+ * drivers/reset/reset-brcmstb.c
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+ * Author: Florian Fainelli <f.fainelli@gmail.com>
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+ * Copyright (C) 2018 Broadcom
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+ */
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+
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+#include <dm.h>
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+#include <errno.h>
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+#include <log.h>
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+#include <malloc.h>
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+#include <reset-uclass.h>
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+#include <asm/io.h>
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+#include <linux/bitops.h>
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+#include <linux/delay.h>
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+
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+#define SW_INIT_SET 0x00
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+#define SW_INIT_CLEAR 0x04
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+#define SW_INIT_STATUS 0x08
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+
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+#define SW_INIT_BIT(id) BIT((id) & 0x1f)
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+#define SW_INIT_BANK(id) ((id) >> 5)
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+
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+/* A full bank contains extra registers that we are not utilizing but still
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+ * qualify as a single bank.
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+ */
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+#define SW_INIT_BANK_SIZE 0x18
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+
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+struct brcmstb_reset_priv {
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+ void __iomem *base;
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+};
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+
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+static int brcmstb_reset_assert(struct reset_ctl *rst)
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+{
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+ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE;
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+ struct brcmstb_reset_priv *priv = dev_get_priv(rst->dev);
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+
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+ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_SET);
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+
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+ return 0;
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+}
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+
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+static int brcmstb_reset_deassert(struct reset_ctl *rst)
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+{
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+ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE;
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+ struct brcmstb_reset_priv *priv = dev_get_priv(rst->dev);
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+
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+ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_CLEAR);
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+ /* Maximum reset delay after de-asserting a line and seeing block
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+ * operation is typically 14us for the worst case, build some slack
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+ * here.
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+ */
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+ udelay(200);
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+
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+ return 0;
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+}
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+
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+struct reset_ops brcmstb_reset_reset_ops = {
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+ .rst_assert = brcmstb_reset_assert,
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+ .rst_deassert = brcmstb_reset_deassert,
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+};
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+
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+static const struct udevice_id brcmstb_reset_ids[] = {
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+ { .compatible = "brcm,brcmstb-reset" },
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+ { /* sentinel */ }
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+};
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+
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+static int brcmstb_reset_probe(struct udevice *dev)
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+{
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+ struct brcmstb_reset_priv *priv = dev_get_priv(dev);
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+
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+ priv->base = dev_remap_addr(dev);
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+ if (!priv->base)
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+ return -EINVAL;
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+
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+ return 0;
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+}
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+
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+U_BOOT_DRIVER(brcmstb_reset) = {
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+ .name = "brcmstb-reset",
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+ .id = UCLASS_RESET,
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+ .of_match = brcmstb_reset_ids,
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+ .ops = &brcmstb_reset_reset_ops,
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+ .probe = brcmstb_reset_probe,
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+ .priv_auto = sizeof(struct brcmstb_reset_priv),
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+};
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