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2 Commits

Author SHA1 Message Date
Greyson Parrelli
7969df4e4c Add basic reglock support to regV5. 2025-12-10 14:41:06 -05:00
Greyson Parrelli
706d89db87 Introduce core-models module. 
Needed to share some key components with feature modules without having
to depend on libsignal-service.
 2025-12-02 16:00:54 -06:00